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compact +30v/15v 256-position digital potentiometer preliminary technical data ad5290 rev. prc information furnished by analog devices is believed to be a ccurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to chan ge without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the proper ty of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. features 256-position +2.7v to +30v single supply operation 2.7v to 15v dual supply operation end-to-end resistance 10 k?, 50 k?, 100 k? low temperature coefficient 35 ppm/c power-on preset to midscale spi compatible interface automotive temperature range C40c to +105c compact msop-10 (3 mm 4.9 mm) package applications programmable gain and offset programmable power supply industrial actuator control led array driver audio volume control general purpose dac replacement mechanical potentiometer replacement general overview the ad5290 is a low cost, compact 2.9 mm 3 mm +30v/15v, 256-position digital potentiometer. this device performs the same electronic adjustment function as mechanical potentiometers or variable resistors, with enhanced resolution, solid-state reliability, and superior low temperature coefficient performance. the wiper settings are controllable through an spi compatible digital interface. the resistance between the wiper and either end point of the fixed resistor varies linearly with respect to the digital code transferred into the rdac latch. the ad5290 is available in 10k, 50k, and 100k ? in compact msop-10 package. ad5290 can be operated from a single supply +2.7 v to +30 v or dual supply 2.7 v to 15 v. all parts are guaranteed to operate over the automotive temperature range of -40c to +105c. functional block diagram ad5290 a w b sdo sdi cs dg nd cl k q d ck rs 8-bit serial reg 8-bit latch 88 v ss v dd por ad5290 a w b sdo sdi cs dg nd cl k q d ck rs 8-bit serial reg 8-bit latch 88 v ss v dd por figure 1. note: the terms digital potentiometer and rdac are used interchangeably.
preliminary technical data ad5290 rev. pr c | page 2 of 11 electrical characteristics10 k?, 50 k?, 100 k? versions (v dd /v ss = 15v10% or 5v10%, v a = +v dd , v b = v ss /0v, -40c < t a < +105c unless otherwise noted) table 1. parameter symbol conditions min typ 1 max unit dc characteristicsrheostat mode resistor differential nonlinearity 2 r-dnl r wb , v a = no connect C1 0.1 +1 lsb resistor integral nonlinearity 2 r-inl r wb , v a = no connect C2 0.25 +2 lsb nominal resistor tolerance 3 ?r ab t a = 25c C30 +30 % resistance temperature coefficient (?r ab /r ab )/?t*10 6 v ab = v dd , wiper = no connect 35 ppm/c wiper resistance r w v dd = 30 v 50 120 ? v dd = 5 v 200 400 ? dc characteristicspotentiometer divider mode resolution n 8 bits differential nonlinearity 4 dnl C1 0.1 +1 lsb integral nonlinearity 4 inl C1 0.3 +1 lsb voltage divider temperature coefficient (?v w /v w )/?t*10 6 code = 0x80 5 ppm/c full-scale error v wfse code = 0xff C3 C1 0 lsb zero-scale error v wzse code = 0x00 0 1 3 lsb resistor terminals voltage range 5 v a,b,w v ss v dd v capacitance 6 a, b c a,b f = 1 mhz, measured to gnd, code = 0x80 45 pf capacitance 6 w c w f = 1 mhz, measured to gnd, code = 0x80 60 pf common-mode leakage i cm v a = v b = v w 1 na digital inputs and outputs input logic high v ih v dd = +5v or +15v 2.4 v input logic low v il v dd = +5v or +15v 0.8 v output logic high v oh r l = 2.2 k ? to +5 v 4.9 v output logic low v ol i ol = 1.6ma, v logic = +5v, v dd = +15v 0.4 v input current i i v in = 0 v or +15 v 1 a input capacitance c i 5 pf power supplies power supply range v dd /v ss dual supply range 2.7 16.5 v power supply range v dd single supply range, v ss = 0 v +2.7 +30 v supply current6 i dd v ih = 5 v or v il = 0 v, v dd = +5 v 0.1 10 a supply current i dd v ih = 5 v or v il = 0 v, v dd = +15 v 0.75 2 ma supply current i ss v ih = 5 v or v il = 0 v, v ss = - 5 v or C15 v 0.02 0.1 ma power dissipation 7 p diss v ih = 5 v or v il = 0 v, v dd = +15 v, v ss = -15 v 11 30 mw power supply sensitivity pss ? v dd = +15v 10%, or ? v ss = -15v 10%, code = midscale 0.01 0.02 %/% dynamic characteristics 6, 8 bandwidth C3db bw r ab = 10 k?/50 k?/100 k?, code = 0x80 525/125/60 khz
preliminary technical data ad5290 rev. pr c | page 3 of 11 total harmonic distortion thd w v a =1 v rms, v b = 0 v, f = 1 khz, r ab = 10 k? 0.05 % v w settling time (10 k?/50 k?/100 k?) t s v a = 5 v, v b = 0 v, 1 lsb error band 4 s resistor noise voltage density e n_wb r wb = 25 k? 14 nv/hz
preliminary technical data ad5290 rev. pr c | page 4 of 11 timing characteristics 10 k? , 50 k?, 100 k? versions (v dd /v ss = 15v10% or 5v10%, v a = +v dd , v b = 0v, -40c < t a < +105c unless otherwise noted.) table 2. parameter symbol conditions min typ 1 max unit spi interface timing characteristics 6, 8,9 (specifications apply to all parts) clock frequency f clk 4 mhz input clock pulsewidth t ch , t cl clock level high or low 120 ns data setup time t ds 30 ns data hold time t dh 20 ns clk to sdo propagation delay t pd r pu = 1k ? , c l < 20pf 10 100 ns cs setup time t css 120 ns cs high pulsewidth t csw 150 ns clk fall to cs fall hold time t csh0 tbd ns clk fall to cs rise hold time t csh1 120 ns cs rise to clock rise setup t cs1 120 ns notes 1. typical specifications represent average readings at +25c and v dd = 5 v. 2. resistor position nonlinearity error r-inl is the deviation fr om an ideal value measured betw een the maximum re sistance and the minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. 3. v ab = v dd , wiper (v w ) = no connect. 4. inl and dnl are measured at v w with the rdac configured as a potentiometer divide r similar to a voltage ou tput d/a converter. v a =v dd and v b =0 v. 5. resistor terminals a, b, w ha ve no limitations on polarity with respect to each other. 6. guaranteed by design and not subject to production test. 7. p diss is calculated from (i dd v dd + i ss v ss ) cmos logic level inputs result in minimum power dissipation. 8. all dynamic characteristics use v dd / v ss = 5 v. 9. see timing diagram for location of measured values. all input control voltages are specified with t r = t f = 2 ns (10% to 90% of 3 v) and timed from a voltage level of 1.5 v.
preliminary technical data ad5290 rev. pr c | page 5 of 11 absolute maximum ratings 1 (t a = +25c, unless otherwise noted.) table 3. parameter value v dd to vss C0.3 v to +33 v v dd to gnd C0.3 v to +33 v v ss to gnd +0.3 v to C16.5 v v a , v b , v w to gnd v ss , v dd maximum current i wb , i wa pulsed i wb continuous (r wb 1 k?, a open) 1 i wa continuous (r wa 1 k?, b open) 1 20 ma 5 ma 5 ma digital inputs voltage to gnd v dd + 0.3 v digital output voltage to gnd 0 v, +30 v operating temperature range C40c to +105c maximum junction temperature (t jmax ) 150c storage temperature C65c to +150c lead temperature (soldering, 10 C 30 sec) 245c thermal resistance 2 ja : msop-10 230c/w notes 1 maximum terminal current is boun ded by the maximum current handling of the switches, maximum power dissip ation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resistance. 2 package power dissipation = (t jmax C t a )/ ja . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
preliminary technical data ad5290 rev. pr c | page 6 of 11 pin configuration and fu nction descriptions 10 9 8 7 1 2 3 4 a b vss w vdd sdo sdi gnd 6 5 clk cs top view ad5290 figure 2. ad5290 pin configuration table 7. ad5290 pin function descriptions pin menmonic description 1 a a terminal. v ss v a v dd 2 b b terminal. v ss v b v dd 3 v ss negative supply. connect to zero volts for single supply applications. 4 gnd digital ground. 5 cs chip select input, active low. when cs returns high, data will be loaded into the wiper register 6 clk serial clock input. positive edge triggered 7 sdi serial data input pin. shifts in one bit at a time on positive clock clk edges. msb loaded first. 8 sdo serial data output pin. internal n-ch fet with open-drain outp ut that requires external pull- up resistor. it shifts out the previous 8 sdi bits that allows daisy-chain operation of multiple packages 9 v dd positive power supply 10 w w terminal. v ss v w v dd
preliminary technical data ad5290 rev. pr c | page 7 of 11 spi interface table 4. ad5290 serial data-word format b7 b6 b5 b4 b3 b2 b1 b0 d7 d6 d5 d4 d3 d2 d1 d0 msb lsb 2 7 2 0 sdi clk cs v out 1 0 1 0 1 0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 rdac register load figure 3. ad5290 spi interface timing diagram (v a = vdd, v b = 0 v, v w = v out ) t csho t css t cl t ch t ds t csw t s t cs1 t csh1 t ch sdi clk cs vout 1 0 1 0 1 0 v dd 0 1lsb (data in) dx dx figure 2. spi interface detailed timing diagram (v a = vdd, v b = 0 v, v w = v out )
preliminary technical data ad5290 rev. pr c | page 8 of 11 operation the ad5290 is a 256-position digitally controlled variable resistor device that can be co ntrolled digitally through spi interface. an internal power-on preset places the wiper at midscale during power-on, which simplifies the fault condition recovery at power-up. determining the variable resistance and voltage rheostat mode operation if only the w-to-b or w-to-a terminals are used as variable resistors, the unused terminal can be opened or shorted with w. this operation is called rheostat mode (figure 3). a w b a w b a w b 03437-0-050 figure 3. rheostat mode configuration the nominal resistance (r ab ) of the rdac has 256 contact points accessed by the wiper terminal, plus the b terminal contact if r wb is considered. the 8-bit data in the rdac latch is decoded to select one of the 256 settings. assuming that a 10 k? part is used, the wipers first connection starts at the b terminal for data 0x00. such connection yields a minimum of 60 ? resistance between terminals w and b because of the 60 ? wiper contact resistance. the second connection is the first tap point, which corresponds to 99 ? ( r wb = (1) r ab /256 + r w ) for data 0x01, and so on. each lsb data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10020 ? ((255) r ab /256 + r w ). figure 6 shows a simplified diagram of the equivalent rdac circuit. the general equation determining r wb is w ab wb r r 256 d ) d ( r + = (1) where: d is the decimal equivalent of the 8-bit binary code. r ab is the end-to-end resistance. r w is the wiper resistance contributed by the on-resistance of the internal switch. table 1. r wb vs. codes; r ab = 10 k? and the a terminal is opened d (dec) r wb (?) output state 255 10020 full-scale (r ab + r w ) 128 5060 midscale 1 99 1 lsb 0 60 zero-scale (wiper contact resistance) since a finite wiper resistance of 60 ? is present in the zero- scale condition, care should be taken to limit the current flow between w and b in this state to a maximum pulse current of no more than 20 ma. otherwise, degradation or possible destruction of the internal switch contact can occur. similar to the mechanical potentiometer, the resistance of the rdac between the wiper w and terminal a also produces a complementary resistance r wa . when these terminals are used, the b terminal can be opened or shorted to w. setting the resistance value for r wa starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. the general equation for this operation is w ab wa r r 256 d 256 ) d ( r + ? = (2) table 2. r wa vs. codes; r ab =10 k? and b terminal is opened d (dec) r wa (?) output state 255 60 full-scale 128 5060 midscale 1 10020 1 lsb 0 10060 zero-scale the typical distribution of the resistance tolerance from device to device is process lot dependent, and it is possible to have 30% tolerance. figure 6. ad5290 equivalent rdac circuit potentiometer mode operation if all three terminals are used, the operation is called the potentiometer mode. the most common configuration is the voltage divider operation (figure 7). b rdac latch and decoder w a r s r s r s r s d7 d6 d4 d5 d2 d3 d1 d0 r w
preliminary technical data ad5290 rev. pr c | page 9 of 11 a v i w b v o 03437-0-051 figure 7. potentiometer mode configuration ignoring the effect of the wiper resistance, the transfer function is simply a w v 256 d ) d ( v = (3) a more accurate calculation, which includes the wiper resistance effect, yields a w w ab w v r 2 r r 256 d ) d ( v + + = ab r (4) if there is an applied voltage at the b terminal, then the transfer function becomes b a w v d v d d v 256 256 256 ) ( ? + = (5) unlike in rheostat mode operation where the absolute tolerance is high, potentiometer mode operation yields an almost ratio- metric function of d/256 with a relatively small error contributed by the rw terms, and therefore the tolerance effect is almost cancelled. although the thin film step resistor r s and cmos switches resistance r w have very different temperature coeffi- cients, the ratiometric adjustment also reduces the overall temperature coefficient effect to 5 ppm/c, except at low value codes where r w dominates. potentiometer mode operations include others such as op amp input, feedback resistor networks, and other voltage scaling applications. a, w, and b terminals can in fact be input or output terminals provided that |v a |, |v w |, and |v b | do not exceed |v dd | and |v ss |. spi compatible 3-wire serial bus the ad5290 contains a 3-wire spi compatible digital interface (sdi, cs , and clk). the 8-bit serial word must be loaded msb first. the format of the word is shown in table . the positive-edge sensitive clk input requires clean transitions to avoid clocking incorrect data into the serial input register. standard logic families work well. cs should start high, when it goes low, the clock loads data into the serial register on each positive clock edge (see figure 3). the data setup and data hold times in the specification table determine the valid timing requirements. the ad5290 uses an 8-bit serial input data register word that is transferred to the internal rdac register when the cs returns to logic high. if dataword contains more than 8-bit, the extra msb bits will be ignored. esd protection all digital inputs are protected with a series input resistor and parallel zener esd structures shown in 8 and figure 9. this applies to the digital input pins sdi, clk, and cs . logic 340 ? v ss figure 8. esd protection of digital pins a,b,w v ss figure 9. esd protection of resistor terminals terminal voltage operating range the ad5290 v dd and gnd power supply defines the boundary conditions for proper 3-terminal digital potentiometer operation. supply signals present on terminals a, b, and w that exceed v dd or gnd will be clamped by the internal forward biased diodes (see figure 10). a v dd b w v ss figure 10. maximum terminal voltages set by v dd and v ss power-up sequence since the esd protection diodes limit the voltage compliance at terminals a, b, and w (see figure 10), it is important to power v dd Cto-gnd and v ss -to-gnd before applying any voltage to terminals a, b, and w; otherwise, the diode will be forward biased such that v dd will be powered unintentionally and may affect the rest of the users circuit. the ideal power-up sequence is in the following order: gnd, v ss ,v dd , digital inputs, and then
preliminary technical data ad5290 rev. pr c | page 10 of 11 v a/b/w . the relative order of powering v a , v b , v w , and the digital inputs is not important as long as they are powered after v dd and v ss with respect to gnd. layout and power supply bypassing it is a good practice to employ compact, minimum lead length layout design. the leads to the inputs should be as direct as possible with a minimum conductor length. ground paths should have low resistance and low inductance. similarly, it is also a good practice to bypass the power supplies with quality capacitors for optimum stability. supply leads to the device should be bypassed with disc or chip ceramic capacitors of 0.01 f to 0.1 f. low esr 1 f to 10 f tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple (see figure 4). note that the digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce. figure 4. power supply bypassing daisy chain operation the serial data output pin (sdo) can be used to daisy chain multiple devices for simultaneous operations, see figure 12. the sdo pin contains an open drain n-ch fet and requires a pull- up resistor. users need to tie the sdo pin of one package to the sdi pin of the next package. if many devices are daisy-chained, users may need to increase the clock period to accommodate the time delay introduced by the pull-up resistors and the capacitive loading at the sdo-sdi interface, see figure 12. if two ad5290 are daisy chained, this requires total 16 bits of data. the first 8 bits goes to u2 and the second 8 bits goes to u1. the cs should be kept low until all 16 bits are clocked into their respective serial registers. the cs is then pulled high to complete the operation. figure 12. daisy chain configuration ad5290 s d i s d o c s c l k ad5290 s d i s d o c s c l k 2 . 2 k ? r p v d d u 1 u 2 s c l k m o s i s s m uc ad5290
preliminary technical data ad5290 rev. pr c | page 11 of 11 outline dimensions 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.00 0.27 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc 3.00 bsc 3.00 bsc 4.90 bsc pin 1 coplanarity 0.10 compliant to jedec standards mo-187ba figure 5. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters ordering guide model 1 r ab (k?) temperature range package description package option branding ad5290yrmz10 10 C40c to +105c msop-10 rm-10 d4u ad5290yrmz10-rl7 10 C40c to +105c msop-10 rm-10 d4u ad5290yrmz50 50 C40c to +105c msop-10 rm-10 d4t AD5290YRMZ50-RL7 50 C40c to +105c msop-10 rm-10 d4t ad5290yrmz100 100 C40c to +105c msop-10 rm-10 d4v ad5290yrmz100-rl7 100 C40c to +105c msop-10 rm-10 d4v ad5290eval evaluation board notes: 1. z in model number denotes lead free package purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge with out detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.

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